The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof. The present invention particularly relates to a technique effectively applied to a semiconductor integrated circuit device including an electrically batch-erasable and rewritable nonvolatile semiconductor memory device (flash memory).
In a manufacturing process of a semiconductor integrated circuit device, when silicon oxide films deposited on a semiconductor substrate are etched to form contact holes, a means is taken to prevent a lower silicon oxide film exposed from each bottom portion of the contact holes, from being excessively etched. As the means, a technique is employed in which a silicon nitride film is provided between an upper layer and a lower layer of the silicon oxide films forming the contact holes, and only the upper layer of the silicon oxide films is etched by using the silicon nitride film as an etching stopper (as disclosed in, for example, Japanese Patent Laid-Open No. 11-26574, etc).
Also, in a manufacturing process of a recent mass storage DRAM (Dynamic Random Access Memory), when contact holes for connecting bit lines and capacitive elements to a semiconductor substrate are formed in spaces of gate electrodes fined, a self align contact (SAC) technique is employed (as disclosed by, for example, Japanese Patent Laid-Open No. 9-252098, etc.). The SAC technique forms the contact holes to be self-aligned to the spaces of the gate electrodes, by constituting an insulating film (referred to as a cap insulating film, a protection insulating film or the like) covering upper portions of the gate electrodes and an insulating film (sidewall insulating film) covering sidewalls of the gate electrodes by silicon nitride films, and by utilizing etching rate difference between the silicon oxide films and the silicon nitride films.
Further, in recent years, the above-mentioned SAC technique has gradually been employed in manufacturing processes of semiconductor memories other than the DRAM. For example, Japanese Patent Laid-Open No. 10-289951 discloses an invention in which the SAC technique is applied to a manufacturing process of an EEPROM (electrically erasable programmable read-only memory).
As a type among flash memories, there is known an NOR type flash memory. Each memory cell of the NOR type flash memory is provided between a gate oxide film and a control gate electrode (word line) located on an upper portion thereof, and is constituted by a so-called floating gate type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a floating gate electrode electrically insulated from the periphery thereof is used as a charge accumulation region. A floating gate type MISFET can relatively reduce a memory size since a control gate electrode (word line) is laminated on an upper portion of a floating gate electrode formed through a thin gate insulating film formed on a main surface of a semiconductor substrate. It can be, therefore, said that the floating gate type MISFET has a memory cell structure suitable for realizing a mass storage.
In the case of the above-mentioned NOR type flash memory, there is a typical method for operation of being written into a memory cell. As the typical method, electrons are injected into the floating gate electrode, and threshold voltage (Vth) of a transistor by using a control gate electrode as a reference voltage is raised in comparison with a state in which no electrons thereof are accumulated. Injection of electrons into the floating gate electrode has, as typical methods, two systems. There is one system in which, by changing a channel current flowing in a source and drain channel to hot electrons in the vicinity of a drain, an electric field of the control gate electrode biased to have a positive voltage makes the hot electrons drown into the floating gate electrode. As another example, there is the other system in which, by a positive voltage applied to a control gate electrode, hot electrons generated by avalanche breakdown in the vicinity of a drain thereof are drown into a floating gate electrode. On the other hand, as a typical example of an erasing operation, there is utilized a system in which, by making electrons FN tunneling (Fowler-Nordheim tunneling) into a gate insulating film below a floating gate electrode, the electrons which are accumulated in the floating gate electrode, the electrons are discharged into the source or drain region of the semiconductor substrate.
Further, in the NOR type flash memory, memory cells are arranged in a lattice shape at respective intersections between predetermined number of word lines extending parallel to one direction and predetermined number of data lines extending parallel to a direction orthogonal to these word lines, the data lines are connected to drain regions of a MISFET constituting each memory cell, and source lines are connected to source regions thereof, respectively. Therefore, if each size of the memory cells is fined in order to make the NOR type flash memory mass storage, then the above-stated SAC technique is indispensable to formation of contact holes for connecting the data lines to the drain regions and that of contact holes for connecting the source lines to the source regions.
However, in the case where the SAC technique is introduced into flash memory manufacturing processes in order to form an insulating film protecting the upper portions of the control gate electrodes out of a silicon nitride film, a silicon nitride film over a control gate electrode gives high stress to a gate oxide film and a substrate of a lower portion thereof and causes crystal defects in the gate oxide film. As a result, it has become clear from consideration of the inventors of the present invention that there arises a problem peculiar to the floating gate type MISFET, the problem being one that charges accumulated in the floating gate electrode easily leak into the substrate.
Taking this disadvantage into account, the inventors of the present invention has considered realization of micro-fabrication memory cell using the SAC technique during suppression of the stress relative to the gate oxide film and the substrate of the lower portion thereof, by forming the protection insulating film over a control gate electrode by a silicon oxide film instead of a silicon nitride film or by a laminating film formed of a silicon oxide film and a silicon nitride film, and then by forming a sidewall insulating film by a silicon nitride film.
However, it has become clear that there arise the following problems of a MISFET manufacturing process in the case of forming the protection insulating film over the control gate electrode by a silicon oxide film. These problems will be described with reference to FIGS. 45 to 50.
To form a MISFET having two-layer gate structure consisting of a floating gate electrode and a control gate electrode, first, a polycrystalline silicon film 102A, an ONO film 103, a polycrystalline silicon film 104A, and a silicon oxide film 105 are sequentially deposited on a gate oxide film 101 formed on the main surface of a semiconductor substrate 100 in this order, as shown in FIG. 45. The polycrystalline silicon film 102A is used for a floating gate. The ONO film 103 consists of a silicon oxide film, a silicon nitride film and a silicon oxide film. The polycrystalline silicon film 104A is used for a control gate. The silicon oxide film 105 is served as a protection insulating film.
Next, as shown in FIG. 46, by using a photoresist film 106 as a mask, the silicon oxide film 105 is dry-etched. After the photoresist film 106 is removed, as shown in FIG. 47, the polycrystalline silicon film 104A, the ONO film 103 and the polycrystalline silicon film 102A which are located below the silicon oxide film 105 are sequentially dry-etched by using the silicon oxide film 105 as a mask. Thereby, floating gate electrodes 102 consisting of the polycrystalline silicon film 102A are formed, and control gate electrodes 104 (word lines WL) consisting of the polycrystalline silicon film 104A are formed.
Next, as shown in FIG. 48, impurity ions are implanted into the semiconductor substrate 100 corresponding to space regions between gate electrodes (floating gate electrodes 102 and control gate electrodes 104). Then, the semiconductor substrate 100 is heat-treated to diffuse the above-mentioned impurities, and thereby impurity introducing regions 107 for constituting source regions and drain regions of the MISFET are formed.
Next, as shown in FIG. 49, the gate oxide film 101 is etched (wet cleaning) by using a hydrofluoric acid solution in order to remove damages generated on the gate oxide film 101 in the gate electrode processing step and the ion implantation step as described above. Since the damages generated on the gate oxide film 101 become paths or the like through which electrons injected into the floating gate electrodes 102 leak from end portions of the floating gate electrodes 102 to the semiconductor substrate 100, degradation of the gate oxide film 101 is caused. It is, therefore, necessary to sufficiently remove the damages by performing this etching (wet cleaning).
However, if the gate oxide film 101 is cleaned by using the hydrofluoric acid solution, the surfaces of the silicon oxide film 105 serving as a protection insulating film which covers the upper portions of the control gate electrodes 104 are also etched simultaneously along with the gate oxide film 101. As a result, as shown in FIG. 49, respective sidewalls of the silicon oxide film 105 retreat toward the central directions of the respective gate electrodes.
Due to this, as shown in FIG. 50, when a silicon nitride film 108 serving as a sidewall insulating film is deposited on the semiconductor substrate 100 in the next step, stepped portions are generated on the silicon nitride film 108 in the vicinity of respective boundaries between each control gate electrode 104 and the silicon oxide film 105. As a result, when contact holes are formed in the space regions of the gate electrodes (floating gate electrodes 102 and control gate electrodes 104) by means of the SAC technique, the silicon nitride film 108 on each stepped portion described above is removed and thickness thereof becomes thin. Thereafter, a problem of defects has occurred such that a metal film embedded into each contact hole and the control gate electrode 104 become closer to each other in the vicinity of each stepped portion described above, and both become short-circuit according to circumstances. The problem like this arises even in the case where the protection insulating film covering the upper portion of each control gate electrode 104 is formed of a laminating film consisting of a silicon oxide film and a silicon nitride film.
As stated above, by consideration of the inventors, it has become clear that if a part of or all of the protection insulating film covering the upper portion of each control gate electrode is formed of a silicon oxide film in order to suppress stress of the gate oxide film and the substrate of the lower portion thereof, the stress being resulted from the silicon nitride film, then it is extremely difficult to realize the micro-fabrication of the MISFET by utilizing the SAC technique.
An object of the present invention is to provide a technique capable of realizing micro-fabrication of a MISFET using the SAC technique while stress resulting from a silicon nitride film and affecting a gate oxide film and a substrate of the lower portion thereof is suppressed.
Another object of the present invention is to provide a technique capable of promoting realization of mass storage and micro-fabrication of a flash memory.
The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
Of inventions disclosed by the present invention, typical embodiments thereof will be described as follows.
According to one embodiment of the present invention, a semiconductor integrated circuit device that is an object includes connection holes (contact holes) whose at least two sides are divided by at least one pair of laminating structure bodies that each are formed over a main surface of a semiconductor substrate to be adjacent to each other and that each consist of a first electrode insulating film, a floating gate electrode, a second gate insulating film, a control gate electrode and a first protection insulating film which are laminated in this order. The above-mentioned first protection insulating film has an etching prevention film at both sidewall portions thereof. When being in an etching step of said first gate insulating film along with the above-mentioned first protection insulating film, this etching prevention film is a substance that is difficult to etch in comparison with the first protection insulating film, that is, a substance that has a different etching rate, or a substance that is in fact not etched. Preferably the above-mentioned first protection insulating film includes a silicon oxide film, and the above-mentioned etching prevention film formed by the sidewall portions thereof is silicon nitride film.
In the case of forming, by a SAC technique, the contact holes in an interlayer insulating film such as a silicon oxide film existing between one pair of laminating structure bodies mentioned above, a thin silicon nitride film for a side spacer is first formed along the entire surfaces of the laminating structure bodies, and the interlayer insulating film is formed on the upper surface thereof so as to embed respective grooves between the laminating structure bodies. Then, relative to the interlayer insulating film like this silicon oxide film, the silicon nitride film which is difficult to etch and which is a side spacer insulating film becoming underlying, is used for etching as a stopper layer (stopper). In this case, when a satisfactory thickness as the etching stopper layer can not be ensured over the side spacer silicon nitride film covering the above-mentioned first protection insulating film, the first protection insulating film may be a laminating film which laminates a silicon nitride film over an upper layer of a silicon oxide film so as to be capable of enduring etching amounts required to form the connection holes of the above-mentioned interlayer insulating film. By doing so, the silicon nitride film of the above-mentioned first protection insulating film can be used as a part of the etching stopper layer. According to the above-stated embodiment, it is possible to omit or reduce use of a protection insulating film material such as a silicon nitride material in which stress affects the semiconductor substrate laminated over the control gate electrode.
According to another embodiment that is the present invention, a method for manufacturing a semiconductor integrated circuit device including an MIS transistor structure on a main surface of a semiconductor substrate is an object, and is characterized by the steps of: forming a first gate insulating film to cover an active region over the main surface of the semiconductor substrate; forming at least one pair of laminating structure bodies which each comprises a floating gate electrode, a second gate insulating film, a control gate electrode and a first protection insulating film which are laminated in this order; introducing impurities for forming a source or a drain through the first gate insulating film exposed between said pair of laminating structure bodies; and removing or cleaning exposed portions of said first gate insulating film given damages in the above-mentioned impurity introduction step, wherein an etching prevention film is formed on the sidewall portions of said first protection insulating film in the step of forming the above-mentioned laminating structure bodies so that the sidewall portions of said first protection insulating film is not retreated in the removing or cleaning step. In a preferable embodiment, the above-mentioned first protection insulating film may include a silicon oxide film, and, for the same reason stated above, may be a laminating film consisting of a silicon oxide film and a silicon nitride film. On the other hand, the above-mentioned etching prevention film covering the sidewall portions of the first protection insulating film is a silicon nitride film. By so constitution, it is possible to omit or reduce use of a protection insulating film material such as a silicon nitride material in which stress thereof affects the semiconductor substrate laminated over the control gate electrode. Further, in the step of removing or cleaning the exposed portion of the above-mentioned first gate insulating film, removing or cleaning of the first gate insulating film exposed below the floating gate electrode can be satisfactorily carried on, in comparison with cleaning in a general transistor manufacturing step. Accordingly, in particular, since the damaged parts of the first gate insulating film can be removed, characteristics of holding information written into a flash memory can be improved.
According to still another embodiment that is the present invention, a method for manufacturing a semiconductor integrated circuit device having an MIS transistor structure of a flash memory includes the steps of:
(a) forming, on a main surface of a semiconductor substrate, a first gate insulating film consisting of a silicon oxide film, and forming a first conductive film, a second gate insulating film and a second conductive film over said first gate insulating film in this order;
(b) forming a first protection insulating film consisting of one of a single layer film and a laminating film, said single layer film being a silicon oxide film formed over said second conductive film, and said laminating film being a silicon nitride film formed over the silicon oxide film;
(c) patterning said first protection insulating film, and thereby forming an etching mask consisting of said first protection insulating film;
(d) patterning said second conductive film, said second gate insulating film and said first conductive film in this order by dry etching using said etching mask as a mask, and thereby forming a plurality of gate electrodes that each have a floating gate electrode consisting of said first conductive film and a control gate electrode consisting of said second conductive film and that each have a laminating structure in which an upper portion of said control gate electrode is covered with said first protection insulating film;
(e) forming a etching prevention film consisting of a silicon nitride film on both sidewall portions of said first protection insulating film patterned, after said step (c) and before said step (d), or after said step (d);
(f) introducing impurities into the main surface of said semiconductor substrate located between sidewall portions facing each other in said plurality of gate electrodes, and thereby forming a source region and a drain region;
(g) treating a surface of said semiconductor substrate by using etchant containing a hydrofluoric acid after said step (f), and thereby cleaning said first gate insulating film located between the sidewall portions which face each other in said plurality of gate insulating film;
(h) covering an upper portion and both sidewall portions of each of said plurality of gate electrodes after said step (g), and forming a second protection insulating film consisting of a silicon nitride film having such a thickness as to partially embed a region between the sidewall portions which face each other in said plurality of gate electrodes;
(i) forming, on an upper portion of said second protection insulating film, an interlayer insulating film consisting of a silicon oxide film, and embedding, with said interlayer insulating film, the region between the sidewall portions which face each other in said plurality of gate electrodes;
(j) etching said interlayer insulating film and said second protection insulating film located between the sidewall portions which face each other in said plurality of gate electrodes, and thereby forming a first connection hole for exposing a surface of said source region and a second connection hole for exposing a surface of said drain region; and
(k) forming a third conductive film electrically connected to said source region inside said first connection hole, and forming a fourth conductive film electrically connected to said drain region inside said second connection hole.
According to this embodiment, since the first protection insulating film covering the upper portion of the control gate electrode is constituted by a silicon oxide film, it is possible to reduce stress which affects the first gate oxide film and the semiconductor substrate which is located below a lower portion thereof, and to suppress generation of crystal defects in the first gate oxide film.
Further, since the etching prevention film consisting of a silicon nitride film is formed over both sidewall portions of the first protection insulating film consisting of the above-mentioned silicon oxide film, it is possible to prevent such drawbacks that the first protection insulating film is etched and retreated when the first gate insulating film is cleaned by etchant containing a hydrofluoric acid.
Moreover, since the first protection insulating film is prevented from retreating, the sidewall portions of the above-mentioned second protection insulating film is prevented from being unnecessarily etched and thereby removed during processing of anisotropic etching of the silicon nitride film which is the second protection insulating film. As a result, as described above with reference to FIG. 50, it is possible to prevent a disadvantage of decrease in withstand voltage between the conductive film being in contact with the drain region or the source region and the control gate electrode, or a disadvantage of short-circuit between those conductors.